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<!@TC:1538936874>
#Build: Synplify Pro (R) N-2018.03G-Beta6, Build 118R, May 15 2018
#install: C:\Gowin\1.8\SynplifyPro
#OS: Windows 8 6.2
#Hostname: BEACONDEV3

# Mon Oct  8 02:27:54 2018

#Implementation: rev_1


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport1></a>Synopsys HDL Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538936875> | Running in 64-bit mode 

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport2></a>Synopsys Verilog Compiler, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538936875> | Running in 64-bit mode 
@N: : <!@TM:1538936875> | : Running Verilog Compiler in System Verilog mode 
@N: : <!@TM:1538936875> | : Running Verilog Compiler in Multiple File Compilation Unit mode 
@I::"C:\Gowin\1.8\SynplifyPro\lib\generic\gw1n.v" (library work)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Gowin\1.8\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\Gowin\gowin-blink\src\demo.v" (library work)
Verilog syntax check successful!
Selecting top level module demo
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="C:\Gowin\gowin-blink\src\demo.v:7:7:7:11:@N:CG364:@XP_MSG">demo.v(7)</a><!@TM:1538936875> | Synthesizing module demo in library work.

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 70MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 02:27:54 2018

###########################################################]

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=compilerReport3></a>Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538936875> | Running in 64-bit mode 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Gowin\gowin-blink\src\demo.v:7:7:7:11:@N:NF107:@XP_MSG">demo.v(7)</a><!@TM:1538936875> | Selected library: work cell: demo view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Gowin\gowin-blink\src\demo.v:7:7:7:11:@N:NF107:@XP_MSG">demo.v(7)</a><!@TM:1538936875> | Selected library: work cell: demo view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 02:27:54 2018

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 02:27:54 2018

###########################################################]

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<!@TC:1538936874>

Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Database state : C:\Gowin\gowin-blink\impl\synthesize\rev_1\synwork\|rev_1
<a name=compilerReport4></a>Synopsys Synopsys Netlist Linker, Version comp2018q1p1, Build 118R, Built May 15 2018 09:18:11</a>

@N: : <!@TM:1538936876> | Running in 64-bit mode 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Gowin\gowin-blink\src\demo.v:7:7:7:11:@N:NF107:@XP_MSG">demo.v(7)</a><!@TM:1538936876> | Selected library: work cell: demo view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="C:\Gowin\gowin-blink\src\demo.v:7:7:7:11:@N:NF107:@XP_MSG">demo.v(7)</a><!@TM:1538936876> | Selected library: work cell: demo view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Mon Oct  8 02:27:56 2018

###########################################################]

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<!@TC:1538936874>
Premap Report


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<!@TC:1538936874>
# Mon Oct  8 02:27:56 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=mapperReport5></a>Synopsys Generic Technology Pre-mapping, Version mapgw, Build 1086R, Built May 17 2018 10:22:59</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1538936878> | No constraint file specified. 
Linked File:  <a href="C:\Gowin\gowin-blink\impl\synthesize\rev_1\fpga_project_scck.rpt:@XP_FILE">fpga_project_scck.rpt</a>
Printing clock  summary report in "C:\Gowin\gowin-blink\impl\synthesize\rev_1\fpga_project_scck.rpt" file 
@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1538936878> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1538936878> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1538936878> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1538936878> | UMR3 is only supported for HAPS-80. 
@N:<a href="@N:MH105:@XP_HELP">MH105</a> : <!@TM:1538936878> | UMR3 is only supported for HAPS-80. 
@N:<a href="@N:MF578:@XP_HELP">MF578</a> : <!@TM:1538936878> | Incompatible asynchronous control logic preventing generated clock conversion. 
syn_allowed_resources : blockrams=10  set on top level netlist demo

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 190MB)



<a name=mapperReport6></a>Clock Summary</a>
******************

          Start                            Requested     Requested     Clock                           Clock                     Clock
Level     Clock                            Frequency     Period        Type                            Group                     Load 
--------------------------------------------------------------------------------------------------------------------------------------
0 -       demo|clk_50M                     100.0 MHz     10.000        inferred                        Autoconstr_clkgroup_0     26   
1 .         demo|clk_led_derived_clock     100.0 MHz     10.000        derived (from demo|clk_50M)     Autoconstr_clkgroup_0     4    
======================================================================================================================================



Clock Load Summary
***********************

                               Clock     Source                  Clock Pin       Non-clock Pin     Non-clock Pin
Clock                          Load      Pin                     Seq Example     Seq Example       Comb Example 
----------------------------------------------------------------------------------------------------------------
demo|clk_50M                   26        clk_50M(port)           clk_led.C       -                 -            
demo|clk_led_derived_clock     4         clk_led.Q[0](dffre)     led[3:0].C      -                 -            
================================================================================================================

<font color=#A52A2A>@W:<a href="@W:MT529:@XP_HELP">MT529</a> : <a href="c:\gowin\gowin-blink\src\demo.v:21:0:21:6:@W:MT529:@XP_MSG">demo.v(21)</a><!@TM:1538936878> | Found inferred clock demo|clk_50M which controls 26 sequential elements including cnt[24:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. </font>

ICG Latch Removal Summary:
Number of ICG latches removed: 0
Number of ICG latches not removed:	0


@S |Clock Optimization Summary



<a name=clockReport7></a>#### START OF PREMAP CLOCK OPTIMIZATION REPORT #####[</a>

1 non-gated/non-generated clock tree(s) driving 26 clock pin(s) of sequential element(s)
1 gated/generated clock tree(s) driving 4 clock pin(s) of sequential element(s)
0 instances converted, 4 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
<a href="@|L:C:\Gowin\gowin-blink\impl\synthesize\rev_1\synwork\fpga_project_prem.srm@|S:clk_50M@|E:cnt[24:0]@|F:@syn_dgcc_clockid0_0==1@|M:ClockId_0_0 @XP_NAMES_BY_PROP">ClockId_0_0</a>       clk_50M             Unconstrained_port     26         cnt[24:0]      
=======================================================================================
============================================================= Gated/Generated Clocks =============================================================
Clock Tree ID     Driving Element     Drive Element Type     Unconverted Fanout     Sample Instance     Explanation                               
--------------------------------------------------------------------------------------------------------------------------------------------------
<a href="@|L:C:\Gowin\gowin-blink\impl\synthesize\rev_1\synwork\fpga_project_prem.srm@|S:clk_led.Q[0]@|E:led[3:0]@|F:@syn_dgcc_clockid0_1==1@|M:ClockId_0_1 @XP_NAMES_BY_PROP">ClockId_0_1</a>       clk_led.Q[0]        dffre                  4                      led[3:0]            Derived clock on input (not legal for GCC)
==================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######

@N: : <!@TM:1538936878> | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1538936878> | Writing default property annotation file C:\Gowin\gowin-blink\impl\synthesize\rev_1\fpga_project.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 190MB)


Finished constraint checker preprocessing (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 190MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 187MB peak: 190MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 103MB peak: 190MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Mon Oct  8 02:27:58 2018

###########################################################]

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<!@TC:1538936874>
Map & Optimize Report


</pre></samp></body></html>
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<!@TC:1538936874>
# Mon Oct  8 02:27:58 2018


Copyright (C) 1994-2018 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: N-2018.03G-Beta6
Install: C:\Gowin\1.8\SynplifyPro
OS: Windows 6.2

Hostname: BEACONDEV3

Implementation : rev_1
<a name=mapperReport8></a>Synopsys Generic Technology Mapper, Version mapgw, Build 1086R, Built May 17 2018 10:22:59</a>


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:<a href="@N:MF916:@XP_HELP">MF916</a> : <!@TM:1538936882> | Option synthesis_strategy=base is enabled.  
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1538936882> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1538936882> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Available hyper_sources - for debug and ip models
	None Found

@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1538936882> | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 190MB)


Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 190MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 190MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 187MB peak: 190MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)


Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		     4.08ns		  48 /        30

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 188MB peak: 190MB)

@N:<a href="@N:FX164:@XP_HELP">FX164</a> : <!@TM:1538936882> | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB)


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 117MB peak: 190MB)

Writing Analyst data base C:\Gowin\gowin-blink\impl\synthesize\rev_1\synwork\fpga_project_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 186MB peak: 190MB)

Writing Verilog Simulation files

Writing scf file... (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 188MB peak: 190MB)

@N:<a href="@N:BW103:@XP_HELP">BW103</a> : <!@TM:1538936882> | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:<a href="@N:BW107:@XP_HELP">BW107</a> : <!@TM:1538936882> | Synopsys Constraint File capacitance units using default value of 1pF  
@A:<a href="@A:BN540:@XP_HELP">BN540</a> : <!@TM:1538936882> | No min timing constraints supplied; adding min timing constraints 

Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 186MB peak: 190MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 187MB peak: 190MB)

<font color=#A52A2A>@W:<a href="@W:MT420:@XP_HELP">MT420</a> : <!@TM:1538936882> | Found inferred clock demo|clk_50M with period 10.00ns. Please declare a user-defined clock on port clk_50M.</font> 
@N:<a href="@N:MT615:@XP_HELP">MT615</a> : <!@TM:1538936882> | Found clock demo|clk_led_derived_clock with period 10.00ns  


<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
<a name=pnr10></a># Timing Report written on Mon Oct  8 02:28:01 2018</a>
#


Top view:               demo
Requested Frequency:    100.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1538936882> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1538936882> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary11></a>Performance Summary</a>
*******************


Worst slack in design: 1.537

                               Requested     Estimated      Requested     Estimated                Clock                           Clock                
Starting Clock                 Frequency     Frequency      Period        Period        Slack      Type                            Group                
--------------------------------------------------------------------------------------------------------------------------------------------------------
demo|clk_50M                   100.0 MHz     118.2 MHz      10.000        8.463         1.537      inferred                        Autoconstr_clkgroup_0
demo|clk_led_derived_clock     100.0 MHz     1314.9 MHz     10.000        0.760         18.479     derived (from demo|clk_50M)     Autoconstr_clkgroup_0
System                         100.0 MHz     866.6 MHz      10.000        1.154         8.846      system                          system_clkgroup      
========================================================================================================================================================





<a name=clockRelationships12></a>Clock Relationships</a>
*******************

Clocks                                                  |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------------------------------------------
Starting                    Ending                      |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------------------------------------------
System                      demo|clk_50M                |  10.000      8.846   |  No paths    -      |  No paths    -      |  No paths    -    
System                      demo|clk_led_derived_clock  |  10.000      8.846   |  No paths    -      |  No paths    -      |  No paths    -    
demo|clk_50M                System                      |  10.000      8.612   |  No paths    -      |  No paths    -      |  No paths    -    
demo|clk_50M                demo|clk_50M                |  10.000      1.537   |  No paths    -      |  No paths    -      |  No paths    -    
demo|clk_led_derived_clock  demo|clk_led_derived_clock  |  10.000      18.479  |  No paths    -      |  No paths    -      |  No paths    -    
===============================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo13></a>Interface Information </a>
*********************

No IO constraint found



====================================
<a name=clockReport14></a>Detailed Report for Clock: demo|clk_50M</a>
====================================



<a name=startingSlack15></a>Starting Points with Worst Slack</a>
********************************

             Starting                                      Arrival          
Instance     Reference        Type     Pin     Net         Time        Slack
             Clock                                                          
----------------------------------------------------------------------------
cnt[17]      demo|clk_50M     DFFC     Q       cnt[17]     0.367       1.537
cnt[15]      demo|clk_50M     DFFC     Q       cnt[15]     0.367       1.604
cnt[12]      demo|clk_50M     DFFC     Q       cnt[12]     0.367       1.747
cnt[3]       demo|clk_50M     DFFC     Q       cnt[3]      0.367       1.814
cnt[11]      demo|clk_50M     DFFC     Q       cnt[11]     0.367       1.814
cnt[2]       demo|clk_50M     DFFC     Q       cnt[2]      0.367       1.881
cnt[13]      demo|clk_50M     DFFC     Q       cnt[13]     0.367       2.024
cnt[18]      demo|clk_50M     DFFC     Q       cnt[18]     0.367       2.024
cnt[4]       demo|clk_50M     DFFC     Q       cnt[4]      0.367       2.091
cnt[16]      demo|clk_50M     DFFC     Q       cnt[16]     0.367       2.091
============================================================================


<a name=endingSlack16></a>Ending Points with Worst Slack</a>
******************************

             Starting                                        Required          
Instance     Reference        Type     Pin     Net           Time         Slack
             Clock                                                             
-------------------------------------------------------------------------------
cnt[6]       demo|clk_50M     DFFC     D       cnt_3[6]      9.867        1.537
cnt[11]      demo|clk_50M     DFFC     D       cnt_3[11]     9.867        1.537
cnt[12]      demo|clk_50M     DFFC     D       cnt_3[12]     9.867        1.537
cnt[13]      demo|clk_50M     DFFC     D       cnt_3[13]     9.867        1.537
cnt[14]      demo|clk_50M     DFFC     D       cnt_3[14]     9.867        1.537
cnt[16]      demo|clk_50M     DFFC     D       cnt_3[16]     9.867        1.537
cnt[18]      demo|clk_50M     DFFC     D       cnt_3[18]     9.867        1.537
cnt[19]      demo|clk_50M     DFFC     D       cnt_3[19]     9.867        1.537
cnt[20]      demo|clk_50M     DFFC     D       cnt_3[20]     9.867        1.537
cnt[21]      demo|clk_50M     DFFC     D       cnt_3[21]     9.867        1.537
===============================================================================



<a name=worstPaths17></a>Worst Path Information</a>
<a href="C:\Gowin\gowin-blink\impl\synthesize\rev_1\fpga_project.srr:srsfC:\Gowin\gowin-blink\impl\synthesize\rev_1\fpga_project.srs:fp:23994:25179:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      8.330
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     1.537

    Number of logic level(s):                4
    Starting point:                          cnt[17] / Q
    Ending point:                            cnt[6] / D
    The start point is clocked by            demo|clk_50M [rising] on pin CLK
    The end   point is clocked by            demo|clk_50M [rising] on pin CLK

Instance / Net              Pin      Pin               Arrival     No. of    
Name               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------
cnt[17]            DFFC     Q        Out     0.367     0.367       -         
cnt[17]            Net      -        -       1.021     -           2         
clk_led4_11        LUT2     I1       In      -         1.388       -         
clk_led4_11        LUT2     F        Out     1.099     2.487       -         
clk_led4_11        Net      -        -       0.766     -           1         
clk_led4_18        LUT4     I0       In      -         3.253       -         
clk_led4_18        LUT4     F        Out     1.032     4.285       -         
clk_led4_18        Net      -        -       0.766     -           1         
clk_led4           LUT3     I1       In      -         5.050       -         
clk_led4           LUT3     F        Out     1.099     6.149       -         
clk_led4           Net      -        -       1.082     -           13        
cnt_3[6]           LUT2     I1       In      -         7.231       -         
cnt_3[6]           LUT2     F        Out     1.099     8.330       -         
cnt_3[6]           Net      -        -       0.000     -           1         
cnt[6]             DFFC     D        In      -         8.330       -         
=============================================================================
Total path delay (propagation time + setup) of 8.463 is 4.829(57.1%) logic and 3.634(42.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport18></a>Detailed Report for Clock: demo|clk_led_derived_clock</a>
====================================



<a name=startingSlack19></a>Starting Points with Worst Slack</a>
********************************

             Starting                                                     Arrival           
Instance     Reference                      Type     Pin     Net          Time        Slack 
             Clock                                                                          
--------------------------------------------------------------------------------------------
led[0]       demo|clk_led_derived_clock     DFFP     Q       led_c[0]     0.367       18.479
led[1]       demo|clk_led_derived_clock     DFFC     Q       led_c[1]     0.367       18.479
led[2]       demo|clk_led_derived_clock     DFFC     Q       led_c[2]     0.367       18.479
led[3]       demo|clk_led_derived_clock     DFFC     Q       led_c[3]     0.367       18.479
============================================================================================


<a name=endingSlack20></a>Ending Points with Worst Slack</a>
******************************

             Starting                                                     Required           
Instance     Reference                      Type     Pin     Net          Time         Slack 
             Clock                                                                           
---------------------------------------------------------------------------------------------
led[0]       demo|clk_led_derived_clock     DFFP     D       led_c[3]     19.867       18.479
led[1]       demo|clk_led_derived_clock     DFFC     D       led_c[0]     19.867       18.479
led[2]       demo|clk_led_derived_clock     DFFC     D       led_c[1]     19.867       18.479
led[3]       demo|clk_led_derived_clock     DFFC     D       led_c[2]     19.867       18.479
=============================================================================================



<a name=worstPaths21></a>Worst Path Information</a>
<a href="C:\Gowin\gowin-blink\impl\synthesize\rev_1\fpga_project.srr:srsfC:\Gowin\gowin-blink\impl\synthesize\rev_1\fpga_project.srs:fp:28672:28909:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      20.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         19.867

    - Propagation time:                      1.388
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 18.479

    Number of logic level(s):                0
    Starting point:                          led[0] / Q
    Ending point:                            led[1] / D
    The start point is clocked by            demo|clk_led_derived_clock [rising] on pin CLK
    The end   point is clocked by            demo|clk_led_derived_clock [rising] on pin CLK
    -Timing constraint applied as multi cycle path with factor 2 (from c:demo|clk_led_derived_clock to c:demo|clk_led_derived_clock)

Instance / Net              Pin      Pin               Arrival     No. of    
Name               Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------
led[0]             DFFP     Q        Out     0.367     0.367       -         
led_c[0]           Net      -        -       1.021     -           2         
led[1]             DFFC     D        In      -         1.388       -         
=============================================================================
Total path delay (propagation time + setup) of 1.521 is 0.500(32.9%) logic and 1.021(67.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
<a name=clockReport22></a>Detailed Report for Clock: System</a>
====================================



<a name=startingSlack23></a>Starting Points with Worst Slack</a>
********************************

                       Starting                                       Arrival          
Instance               Reference     Type     Pin     Net             Time        Slack
                       Clock                                                           
---------------------------------------------------------------------------------------
clk_led_i_i            System        INV      O       clk_led_i_i     0.000       8.846
rst_n_ibuf_RNIBNDC     System        INV      O       rst_n_c_i       0.000       8.846
=======================================================================================


<a name=endingSlack24></a>Ending Points with Worst Slack</a>
******************************

             Starting                                           Required          
Instance     Reference     Type      Pin        Net             Time         Slack
             Clock                                                                
----------------------------------------------------------------------------------
clk_led      System        DFFCE     D          clk_led_i_i     9.867        8.846
led[0]       System        DFFP      PRESET     rst_n_c_i       9.867        8.846
==================================================================================



<a name=worstPaths25></a>Worst Path Information</a>
<a href="C:\Gowin\gowin-blink\impl\synthesize\rev_1\fpga_project.srr:srsfC:\Gowin\gowin-blink\impl\synthesize\rev_1\fpga_project.srs:fp:31773:32013:@XP_NAMES_GATE">View Worst Path in Analyst</a>
***********************


Path information for path number 1: 
      Requested Period:                      10.000
    - Setup time:                            0.133
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         9.867

    - Propagation time:                      1.021
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 8.846

    Number of logic level(s):                0
    Starting point:                          clk_led_i_i / O
    Ending point:                            clk_led / D
    The start point is clocked by            System [rising]
    The end   point is clocked by            demo|clk_50M [rising] on pin CLK

Instance / Net               Pin      Pin               Arrival     No. of    
Name               Type      Name     Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------
clk_led_i_i        INV       O        Out     0.000     0.000       -         
clk_led_i_i        Net       -        -       1.021     -           1         
clk_led            DFFCE     D        In      -         1.021       -         
==============================================================================
Total path delay (propagation time + setup) of 1.154 is 0.133(11.5%) logic and 1.021(88.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 188MB peak: 190MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 188MB peak: 190MB)

---------------------------------------
<a name=resourceUsage26></a>Resource Usage Report for demo </a>

Mapping to part: gw1n_4lqfp144-6
Cell usage:
ALU             25 uses
DFFC            28 uses
DFFCE           1 use
DFFP            1 use
GSR             1 use
INV             2 uses
LUT2            13 uses
LUT3            1 use
LUT4            7 uses

I/O ports: 6
I/O primitives: 6
IBUF           2 uses
OBUF           4 uses

I/O Register bits:                  0
Register bits not including I/Os:   30 of 3456 (0%)
Total load per clock:
   demo|clk_50M: 26
   demo|clk_led_derived_clock: 4

@S |Mapping Summary:
Total  LUTs: 21 (0%)

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 37MB peak: 190MB)

Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Mon Oct  8 02:28:02 2018

###########################################################]

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